The present invention relates to a hardware logic simulator.
Conventional software logic simulators operated by computer programs have been used to examine the design of logic circuits each comprising a large number of logic gates.
In recent years, various types of hardware logic simulators have been proposed in place of software logic simulators since software logic simulators require a long simulation execution time and a large volume of test data relating to the design of a logic circuit such as a large scale integrated circuit (LSI) including numerous gates.
A hardware logic simulator generally comprises a memory for creating a simulation model including types of gates included in a logic circuit to be simulated, connections between the gates, and latest states of output signals from the gates, and a simulation execution section for causing the simulation model to perform logic operations using test data corresponding to various test cases.
One of the measures for the quality of simulation is the degree of completeness of simulation, i.e., the degree of simulation capable of effectively executing all cases which may occur in actual operations of the logic circuit as an objective for simulation within a short period of time and a small number of operation steps.
It is actually difficult to check the completeness of simulation in, especially, an LSI hardware logic simulator. As a result, the number of cases tested is often too small and logical errors are found after the fabrication of LSIs. In addition, identical test cases are often repeatedly tested, thus wasting effort.